ECE seminar: Next-gen VLSI Ed-tech
This event is in the past.
1 p.m. to 2 p.m.
Next-gen VLSI Ed-tech: Open Source tools, RISC-V design, SKY130nm open-PDKs, no NDA, no legal, just clone and learn.
Kunal Ghosh, Director and co-founder of VLSI System Design (VSD)
The field of Very Large-Scale Integration (VLSI) is rapidly evolving, and education in this area is becoming more important than ever. However, traditional education models in VLSI have been constrained by high costs, proprietary design tools, legal constraints, and restrictive Non-Disclosure Agreements (NDAs). In this talk, we introduce a new paradigm for VLSI education that leverages the power of open-source tools, RISC-V design, SKY130nm open-Process Design Kits (PDKs), and a clone-and-learn approach that requires no NDA or legal constraints.
We will first introduce the audience to the concept of RISC-V design, an open-source instruction set architecture that is rapidly gaining popularity in the VLSI community. We will then discuss the SKY130nm open-PDK, which is a fully open-source process design kit for the 130nm process node, including design rules, layout, and SPICE models. We will show how this PDK can be used to design basic digital circuits, such as gates and flip-flops, and more complex circuits, such as microprocessors.
Finally, we will demonstrate how a clone-and-learn approach can be used to teach VLSI design. Instead of relying on expensive proprietary tools and NDAs, students can clone existing designs and modify them to learn how to design VLSI circuits. We will provide examples of open-source designs that can be cloned and modified, as well as resources for learning more about VLSI design using open-source tools and the RISC-V architecture.
Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD)., a cloud-based ed-tech learning platform for VLSI education, which has trained close to 80,000+ VLSI engineers across 152+ countries in 40+ different languages. VSD has worked with top institutes of the country, like IIT Madras, IIT Bombay, and IIT Guwahati for various Faculty Development Program (FDPs), which has trained close to 6000+ students within India. VSD community owns the largest open-source analogue, digital and mixed-signal IPs using Skywater 130nm technology node, which is FREE for anyone around the globe to download and learn. The VSD-trained community has done more than 40+ tapeouts, which is very rare for a training company. Before launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm's Test-chip business unit. Kunal joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, and 16nm test chips. In 2013, he joined Cadence as the Lead Sales Application engineer for the Tempus STA tool. Kunal holds a Master's degree in Electrical Engineering from the Indian Institute of Technology (IIT), Bombay, India, specializing in VLSI Design & Nanotechnology. Kunal was a Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm. He was also a Research Assistant with Prof. Madhav Desai, to characterize RTL, generated from the C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from the AHIR compiler, through standard ASIC toolchains like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software.